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A directory of Western Digital’s RISC-V SweRV Cores
Ariane is a 6-stage RISC-V CPU capable of booting Linux
The root repo for lowRISC project and FPGA demos.
An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
A Verilog synthesis flow for Minecraft redstone circuits
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
RISC-V CPU Core
Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
Contains the code examples from The UVM Primer Book sorted by chapters.
training labs and examples
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Reference examples and short projects using UVM Methodology
Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
Ultimate multigame cartridge for Nintendo Famicom
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Source code repo for UVM Tutorial for Candy Lovers
Verilog code for a simple synth module; developed on TinyFPGA BX
Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
a playground for xilinx zynq fpga experiments
Hardware of sampling model