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  1. A directory of Western Digital’s RISC-V SweRV Cores

    SystemVerilog 671 80 Built by @aprnath @parthpower @0xflotus @manegspb @tomverbeure
  2. Ariane is a 6-stage RISC-V CPU capable of booting Linux

    SystemVerilog 468 78 Built by @zarubaf @msfschaffner @stmach @jrrk @Moschn
  3. The root repo for lowRISC project and FPGA demos.

    SystemVerilog 388 83 Built by @wsong83 @jrrk @wallento @furkanturan @luismarques
  4. An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.

    SystemVerilog 291 24 Built by @wickedfoo
  5. A Verilog synthesis flow for Minecraft redstone circuits

    SystemVerilog 230 4 Built by @itsFrank @Omar-Bamashmos @orta
  6. RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

    SystemVerilog 200 78 Built by @atraber @davideschiavone @svenstucki @bluewww @gautschimi
  7. SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    SystemVerilog 190 56 Built by @dp-sc @ar-sc
  8. RISC-V CPU Core

    SystemVerilog 124 23 Built by @rherveille @sphardy @frantony
  9. training labs and examples

    SystemVerilog 124 76 Built by @mramdas @mayur13
  10. Contains the code examples from The UVM Primer Book sorted by chapters.

    SystemVerilog 114 65 Built by @rdsalemi @raysalemi
  11. CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

    SystemVerilog 81 19 Built by @tymonx @gitter-badger @Velik123
  12. Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs

    SystemVerilog 66 15 Built by @michael-adler @nakulkorde @luebbers @rahulrs
  13. Reference examples and short projects using UVM Methodology

    SystemVerilog 65 67 Built by @mramdas @robingarg89 @mayur13
  14. This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

    SystemVerilog 64 22 Built by @davideschiavone @bluewww @haugoug @FrancescoConti @politicante
  15. SystemVerilog 63 22 Built by @taoliug @scottj97 @mgielda
  16. Ultimate multigame cartridge for Nintendo Famicom

    SystemVerilog 59 15 Built by @ClusterM
  17. Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

    SystemVerilog 58 37 Built by @Atokulus @atraber @svenstucki @davideschiavone @vogelpi
  18. This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

    SystemVerilog 53 21 Built by @haugoug @anga93 @davideschiavone @politicante @FrancescoConti
  19. Source code repo for UVM Tutorial for Candy Lovers

    SystemVerilog 52 36 Built by @cluelogic
  20. Verilog code for a simple synth module; developed on TinyFPGA BX

    SystemVerilog 49 3 Built by @gundy @lawrie
  21. Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

    SystemVerilog 44 21 Built by @kbrunham-intel @ycai-intel @fjavaher
  22. SystemVerilog 43 20 Built by @nosnhojn @jesseprusi @B00Ze @tudortimi @daveread4
  23. Public repository for uEVB

    SystemVerilog 41 9 Built by @RHSResearchLLC
  24. High performance embedded systems debug/reverse engineering platform

    SystemVerilog 40 5 Built by @azonenberg
  25. a playground for xilinx zynq fpga experiments

    SystemVerilog 40 6 Built by @swetland @travisg
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