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Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.
SERV - The SErial RISC-V CPU
MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
PicoRV32 - A Size-Optimized RISC-V CPU
RTL, Cmodel, and testbench for NVDLA
The Ultra-Low Power RISC Core
opensouce RISC-V implemented from scratch in one night!
An open source GPU based off of the AMD Southern Islands ISA.
Silicon proven Verilog library for IC and FPGA designers
HDL libraries and projects
A small, light weight, RISC CPU soft core
MIPS CPU implemented in Verilog
mor1kx - an OpenRISC 1000 processor IP core
🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board
A litecoin scrypt miner implemented with FPGA on-chip memory.
Verilog Ethernet components
Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux
High performance motor control
NetFPGA 1G infrastructure and gateware
VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".
An open source library for image processing on FPGA.
RISC-V Formal Verification Framework
Open source implementation of a x86 processor
Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks
Repository for basic (and not so basic) Verilog blocks with high re-use potential