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  1. Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

    Verilog 128 9 Built by @rajeevsharma1 12 stars today
  2. SERV - The SErial RISC-V CPU

    Verilog 50 6 Built by @olofk 5 stars today
  3. MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

    Verilog 883 43 Built by @mntmn @stephanIOA @jlandheer
  4. PicoRV32 - A Size-Optimized RISC-V CPU

    Verilog 803 201 Built by @cliffordwolf @wallclimber21 @olofk @thoughtpolice @frantony
  5. RTL, Cmodel, and testbench for NVDLA

    Verilog 700 253 Built by @zdraw @jwise @shallyou @nvdsmith @xalogic-linus
  6. The Ultra-Low Power RISC Core

    Verilog 627 258 Built by @SI-RISCV @zhenbohu @myron2009
  7. opensouce RISC-V implemented from scratch in one night!

    Verilog 584 38 Built by @samsoniuk @erjanmx @phuclv90
  8. An open source GPU based off of the AMD Southern Islands ISA.

    Verilog 503 126 Built by @zwabbit @d1duarte @vinaygangadhar @stanso @tchamberlain71
  9. Silicon proven Verilog library for IC and FPGA designers

    Verilog 424 146 Built by @aolofsson @olajep @peteasa @plindstroem @wasserfuhr
  10. HDL libraries and projects

    Verilog 336 603 Built by @rkutty @Csomi @acostina @larsclausen @AndreiGrozav
  11. A small, light weight, RISC CPU soft core

    Verilog 297 27 Built by @ZipCPU @foobar2016
  12. MIPS CPU implemented in Verilog

    Verilog 270 116 Built by @jmahler @ppisa
  13. mor1kx - an OpenRISC 1000 processor IP core

    Verilog 250 98 Built by @skristiansson @juliusbaxter @wallento @stffrdhrn @olofk
  14. 🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

    Verilog 236 69 Built by @Obijuan @AntonioMR @Jesus89 @adumont
  15. A litecoin scrypt miner implemented with FPGA on-chip memory.

    Verilog 224 103 Built by @kramble @C-Elegans
  16. Verilog Ethernet components

    Verilog 223 73 Built by @alexforencich
  17. Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux

    Verilog 220 84 Built by @Obijuan @Testato @mattvenn @Jesus89 @ZioGuillo
  18. High performance motor control

    Verilog 206 88 Built by @madcowswe @jtmorris245
  19. NetFPGA 1G infrastructure and gateware

    Verilog 200 110 Built by @grg @ericklo @divinekumar @rkerur @eastzone
  20. VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

    Verilog 198 47 Built by @sergeykhbr @denisnefedov @vepr-y @jrrk @mateoconlechuga
  21. An open source library for image processing on FPGA.

    Verilog 185 98 Built by @dtysky
  22. RISC-V Formal Verification Framework

    Verilog 179 13 Built by @cliffordwolf @Dolu1990 @tomverbeure @yx9527
  23. Open source implementation of a x86 processor

    Verilog 176 47 Built by @marmolejo @sirchuckalot @ys05 @oppernerd @AlteraFreak
  24. Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

    Verilog 172 30 Built by @danielholanda @baharsalehpour @joseppinilla @LucasBraganca @santacml
  25. Repository for basic (and not so basic) Verilog blocks with high re-use potential

    Verilog 160 59 Built by @seldridge
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