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  1. MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

    Verilog 895 47 Built by @mntmn @stephanIOA @andrej-mntmn @jlandheer
  2. PicoRV32 - A Size-Optimized RISC-V CPU

    Verilog 867 228 Built by @cliffordwolf @wallclimber21 @olofk @thoughtpolice @frantony
  3. RTL, Cmodel, and testbench for NVDLA

    Verilog 741 268 Built by @zdraw @jwise @shallyou @nvdsmith @xalogic-linus
  4. The Ultra-Low Power RISC Core

    Verilog 729 308 Built by @SI-RISCV @zhenbohu @myron2009
  5. opensouce RISC-V implemented from scratch in one night!

    Verilog 614 49 Built by @samsoniuk @erjanmx @phuclv90
  6. An open source GPU based off of the AMD Southern Islands ISA.

    Verilog 520 129 Built by @zwabbit @d1duarte @vinaygangadhar @stanso @tchamberlain71
  7. Silicon proven Verilog library for IC and FPGA designers

    Verilog 448 155 Built by @aolofsson @olajep @peteasa @plindstroem @wasserfuhr
  8. HDL libraries and projects

    Verilog 368 639 Built by @rkutty @Csomi @acostina @larsclausen @AndreiGrozav
  9. A small, light weight, RISC CPU soft core

    Verilog 333 35 Built by @ZipCPU @foobar2016
  10. SD card based multi-purpose cartridge for the SNES

    Verilog 300 72 Built by @mrehkopf @RedGuyyyy @borti4938 @francois-berder @Godzil
  11. MIPS CPU implemented in Verilog

    Verilog 294 122 Built by @jmahler @ppisa
  12. mor1kx - an OpenRISC 1000 processor IP core

    Verilog 262 102 Built by @skristiansson @juliusbaxter @stffrdhrn @wallento @olofk
  13. Verilog Ethernet components

    Verilog 257 84 Built by @alexforencich
  14. 🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

    Verilog 244 74 Built by @Obijuan @AntonioMR @Jesus89 @adumont
  15. Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux

    Verilog 233 89 Built by @Obijuan @Testato @mattvenn @Jesus89 @ZioGuillo
  16. A litecoin scrypt miner implemented with FPGA on-chip memory.

    Verilog 226 106 Built by @kramble @C-Elegans
  17. High performance motor control

    Verilog 225 95 Built by @madcowswe @jtmorris245
  18. VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

    Verilog 215 49 Built by @sergeykhbr @denisnefedov @vepr-y @jrrk @mateoconlechuga
  19. An open source library for image processing on FPGA.

    Verilog 209 106 Built by @dtysky
  20. Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

    Verilog 208 39 Built by @danielholanda @baharsalehpour @joseppinilla @LucasBraganca @santacml
  21. NetFPGA 1G infrastructure and gateware

    Verilog 208 117 Built by @grg @ericklo @divinekumar @rkerur @eastzone
  22. Defines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.

    Verilog 191 15 Built by @rajeevsharma1 @michaelgmcintyre
  23. RISC-V Formal Verification Framework

    Verilog 190 17 Built by @cliffordwolf @Dolu1990 @AlAlves @tomverbeure @yx9527
  24. Open source implementation of a x86 processor

    Verilog 183 47 Built by @marmolejo @sirchuckalot @ys05 @oppernerd @AlteraFreak
  25. Repository for basic (and not so basic) Verilog blocks with high re-use potential

    Verilog 182 64 Built by @seldridge
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